Wafer chuck, exposure system, and method of manufacturing semiconductor device

ABSTRACT

In a wafer chuck for flatly vacuum-chucking a semiconductor wafer ( 11 ) supported by support pins ( 15 ) such that a pressure in a suction chamber ( 13 ) surrounded by an external wall ( 12 ), the upper surface of the external wall ( 12 ) is formed to be lower than the upper surfaces of the support pins, and the upper surface of the external wall ( 12 ) does not pressure the semiconductor wafer ( 11 ), a distance (L1) between the external wall ( 12 ) and closest support pins ( 15   a ) is up to 1.8 mm, and an alignment pitch (L2) of the support pins ( 15 ) aligned inside the closest support pins ( 15 a) to the external wall ( 12 ) is not more than 1.5 times of the distance (L1) between the external wall ( 12 ) and the closest support pins ( 15   a ).

TECHNICAL FIELD

[0001] The present invention relates to a wafer chuck and an exposuretechnique which use the wafer chuck, and to a manufacturing technique ofsemiconductor device and, more particularly, to a technique which iseffectively applied to a wafer chuck or the like used forvacuum-chucking a semiconductor wafer in the steps in manufacturing asemiconductor device.

BACKGROUND ART

[0002] For example, in an exposure system which coats a resist on asemiconductor wafer and which exposes and develops a circuit pattern ofone layer formed on a reticle serving as an original so as to form apredetermined resist pattern on the semiconductor wafer, the degree offlatness of the semiconductor wafer is an important technical object inorder to prevent resolving defects caused by not obtaining an imageformation within a focal depth and to form a sharp circuit pattern. Forthis reason, a flat state of the semiconductor wafer is to be requiredby such a way that the wafer is vacuum-chucked from the rear surfacethereof by a wafer chuck having a high degree of flatness. An exposureprocess is performed to the wafer.

[0003] As an example in which such an exposure system is described indetail, “VLSI MANUFACTURING AND TEST DEVICE GUIDEBOOK IN 1998” issued byKogyo Chosakai Publishing Co., Ltd. (Nov. 20, 1997) is known. The waferchuck has a configuration in which a large number of support pins areimplanted inside a cap-like vessel. However, in this structure, theouter peripheral wall of the cup-like vessel and the large number ofsupport pins are brought into contact with the rear surface of thesemiconductor wafer so as to apply the negative pressure into thecap-like vessel, thereby supporting the semiconductor wafer. Therefore,warpage of the peripheral portion of the semiconductor wafer is notsufficiently corrected. Since micropatterning in a process makes thefocal depth further small, flattening a semiconductor wafer in exposurebecomes an important technical object every year.

[0004] With respect to the art, as an important which increases thedegree of flatness in the peripheral portion of a semiconductor wafer,an art disclosed in Japanese Patent Application Laid-Open No. 8-37227 isknown. This art can achieve a predetermined effect such an in correctionof upward warping transformation at the peripheral portion of thesemiconductor wafer.

DISCLOSURE OF THE INVENTION

[0005] However, in the wafer chuck described in the above conventionalart, a sufficient degree of flatness cannot be achieved. Morespecifically, when a wafer is warped reversely (downwardly) in the aboveinvention, the invention does not disclose a predetermined relationshipin shape which corrects the warpage so that wafer correction forrealizing a high degree of flatness in the entire area of thesemiconductor wafer has a given limit.

[0006] It is an object of the present invention to provide a techniquewhich can more effectively prevent warpage of a semiconductor wafervacuum-chucked on a wafer check and which can realize a high degree offlatness of the entire area of the semiconductor wafer.

[0007] It is another object of the present invention to provide atechnique which can vacuum-chuck semiconductor wafers having variousdiameters on single wafer chuck.

[0008] It is still another object of the present invention to provide atechnique which can improve the manufacturing yield of semiconductordevices.

[0009] The above objects and other objects of the present invention andnovel characteristic features will be apparent from the description ofthis specification and the accompanying drawings.

[0010] The outline of typical one of the aspects of the presentinvention will be briefly described below.

[0011] More specifically, a wafer chuck according to the presentinvention is adopted to flatly vacuum-chucks a semiconductor waferhaving a rear surface which is held on support pins by suction with asuction chamber at a negative pressure applied thereto, the suctionchamber surrounded by an external wall, wherein the upper surface of theexternal wall is formed to have a level slightly lower than those of theupper surfaces of the support pins; the external wall does not chuck thesemiconductor wafer and does not in contact with the semiconductorwafer; and air is slightly sucked into the suction chamber.

[0012] In addition, the wafer chuck is characterized in that thedistance between the external wall and the closest support pin is keptconstant, a moment is generated such that the gradient of thesemiconductor wafer being in contact with the outermost closest supportpin is small, and flexure of the semiconductor wafer caused by vacuum isminimum.

[0013] An exposure system according to the present invention ischaracterized by being constituted by using the wafer chuck.

[0014] A method of manufacturing a semiconductor device according to thepresent invention applies the wafer chuck to the step of polishing asemiconductor wafer and an exposure system for exposing thesemiconductor wafer to manufacture a semiconductor device.

[0015] According to the wafer chuck having the above constitution,inflow air generates a pressure loss by the external wall to make thepressure in the suction chamber negative, a vacuum pressure between theexternal wall and the closest support pin is generated by the negativepressure. When a moment generated by the vacuum pressure is equal tomoment acting on the internal side of the closest support pin, the waferis not inclined at a position above the closest support pin because themoments are balanced.

[0016] In addition, when the distance between the external wall and theclosest support pin is not more than a predetermined distance, flexureor gradient of the wafer from the closest support pin to an externalbank can be made sufficiently small. For this reason, the degree offlatness of the wafer near the peripheral portion of the wafer can bemaintained at high accuracy.

[0017] According to the exposure system using the wafer chuck describedabove, even in a micropatterning process having a small focal depth, apreferable circuit pattern can be transferred to a semiconductor wafer.

[0018] According to the method of manufacturing a semiconductor usingthe wafer chuck or the exposure system, a semiconductor device can bemanufactured even in a micropatterning process having a small focaldepth.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a conceptual diagram showing an exposure system using awafer chuck according to an embodiment of the present invention.

[0020]FIG. 2 is a perspective view showing the wafer chuck according tothe embodiment of the present invention and a semiconductor wafer.

[0021]FIG. 3 is a plan view of the wafer chuck according to theembodiment of the present invention.

[0022]FIG. 4 is a schematic sectional view of a part along a line A-A inFIG. 3.

[0023]FIG. 5 is a sectional view showing a modification of the waferchuck according to the embodiment of the present invention.

[0024]FIG. 6 is a plan view showing a modification of the wafer chuckaccording to the embodiment of the present invention.

[0025]FIG. 7 is a flow chart showing an example of a method ofmanufacturing a semiconductor device according to the embodiment of thepresent invention.

[0026]FIG. 8 is a diagram for explaining an example of the operation ofthe wafer chuck according to the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0027] Embodiments of the present invention will be described below indetail with reference to the drawings.

[0028] (Embodiment 1)

[0029]FIG. 1 is a schematic diagram showing an exposure system using awafer chuck according to an embodiment of the present invention, FIG. 2is a perspective view showing the wafer chuck and a semiconductor wafer,FIG. 3 is a plan view of the wafer chuck in FIG. 2, and FIG. 4 is aschematic sectional view of a part along a line A-A in FIG. 3.

[0030] As shown in FIG. 1, an exposure system provided with a waferchuck uses, for example, an Hg lamp 2 as an exposure light source.Exposure light 3 emitted from the Hg lamp 2 is converged by an ellipticmirror 4 and then converged by a condensing lens 8 through a reflector5, a relay lens 6, and a reflector 7. The light passing through theillumination system takes a circuit pattern formed in a reticle 9, andis reduced by a reduction lens 10, so that the light is finallyprojected on a semiconductor wafer 11 chucked by a wafer chuck 1. Inthis manner, the circuit pattern is transferred onto the semiconductorwafer 11 on which a resist is coated.

[0031] The wafer chuck 1 is comprised of a material such as ceramics toprevent transformation caused by aging or thermal expansion and isarranged to chuck the semiconductor wafer 11. As shown in FIG. 2, thewafer chuck includes a suction chamber 13 which is surrounded by anexternal wall 12 and which is formed in a chuck body 14. The suctionchamber 13 is connected to an external exhaust pump or the like (notshown) through a suction hole 16. As shown in FIG. 3, the external wall12 is formed to have a size which is slightly smaller than that of thesemiconductor wafer 11, and is curved to the rear surface of thesemiconductor wafer 11 to prevent adhesion or the like of the coatedresist solution.

[0032] The upper surface of the external wall 12 is designed to beslightly lower than the level of a plurality of support pins 15 whichsupport the semiconductor wafer 11 from its rear surface. The rearsurface of the semiconductor wafer 11 and the upper surface of theexternal wall 12 have a small gap 5. Therefore, the suction chamber 13from which air is exhausted through the suction hole 16 communicateswith the outside through the gap. A leakage flow rate Q is expressed bythe following equation from theoretical calculation and an experimentalresult.

Q=3bδ ³/4 μ·dp/dx  (Equation 1)

[0033] where, b: peripheral length of external wall, δ: gap, μ:viscosity coefficient, dP/dx: pressure gradient.

[0034] As shown in Equation 1, when the gap is made small, the viscosityof air flowing in the gap strongly acts, and a pressure loss generatedwhen air passes through the external wall 12 (vacuum seal is establishedfrom when the pressure loss is generated).

[0035] As an experimental example, the semiconductor wafer 11 (rearsurface is satin-finished) having a diameter φ of 200 was used, thewidth of the external wall 12 was 0.3 mm, the gap δ was 0.5 μm, and thepressure of a vacuum source was 0.79 kPa (600 mmHg). In this case, adecrease in pressure caused by inflow of air from the external wall 12was 3.2%. In the same way, a decrease in pressure in a conventionalstructure in which the external wall 12 was in contact with a pin was1.3%. When the width of the external wall 12 and the gap δ are changed,a decrease in pressure can be controlled. For this reason, the waferchuck 1 which copes with a change in diameter of the semiconductor wafer11 can be manufactured.

[0036] When the semiconductor wafer 11 are supported by thesharp-pointed support pins 15, the pressing pressures are generated atthe tops of the support pins 15 due to a pressure difference dP betweenthe pressure of the suction chamber 13 and the atmospheric pressure.However, it is experientially known that a result is obtained on theassumption that transformation of a portion pressed by a continuoussurface such as the surface of the external wall 12 is different fromtransformation of a portion pressed by the tops of the support pins 15.This difference is related to a vacuum pressure, the areas of the topsof the pins, the arrangement of pins, the condition of the rear surfaceof the semiconductor wafer 11, and the like.

[0037] In this embodiment, although no continuous contact portion isprovided between the rear surface of the semiconductor wafer 11 and theupper surface of the external wall 12, the arrangement of the supportpins 15 must be considered. When the alignment pitches of the supportpins 15 are set as equal as possible, and when closest support pins 15 ato the external wall 12 is arranged to receive vacuum pressures whichare equal to each other, the highest degree of flatness can be obtainedregardless of the condition of the rear surface of the semiconductorwafer 11. More specifically, the support pins 15 a may be arranged suchthat a distance (distance L1) between the external wall 12 and theclosest support pin 15 a is almost equal to half an alignment pitch L2of the support pins 15. When an accuracy error of within ±50 nm is seton a target, the alignment pitch L2 of the internal support pins 15 andthe distance L1 between the external wall 12 and the closest support pin15 a desirably satisfy a relation: L2/6≦L1≦L2.

[0038] The relation between the distance L1 between the external wall 12and the closest support pins 15 a and the alignment pitch L2 of theinternal support pins 15 can be applied to not only alignment pitches ina radial direction of the wafer chuck as described above but alsoalignment pitches in a circumferential direction.

[0039] More specifically, from a viewpoint that the pressures receivedby the support pins are set as equal as possible, the alignment pitch L2is set to be not more than 1.5 times the distance L1 between theexternal wall 12 and the closest support pins 15 a for the followingreason.

[0040] It must be necessary for realizing a high degree of flatness ofthe semiconductor wafer 11 that pressures acting on the tops of thesupport pins 15 are set as equal as possible. That is, in vacuumchucking, an area on which the atmospheric pressure acts is equallyshared by the support pins 15.

[0041] In particular, a problem is outstandingly posed at a peripheralportion (internal wall 17) of a press-up hole 18 into/from which apress-up pin 19 for pressing the semiconductor wafer 11 illustrated inFIG. 5 (to be described later) enters. Especially, pressures acting onthe tops of the closest support pins 15 a to the internal wall 17 isconsiderably influenced on the degree of flatness.

[0042] An experimental check for forecasting distortion is performedwith respect to this influence.

[0043] In the experiment, as illustrated in FIG. 8, the ratio of thedensity of alignment of the closest support pins 15 a which were closestto the internal wall 17 to the density of alignment of support pins 15 bwhich were adjacently outside the alignment of the closest support pins15 a was changed to 1.5 times, and the ratio of a pressure P1 (pressureof area {circle over (1)}) acting on the top of the support pin 15 a toa pressure P2 (pressure of area {circle over (2)}) acting on the top ofthe support pin 15 b was set to be 1.5 times to 1/1.5 times. In thiscase, a distortion of about 90 nm was measured. Since the distortion is100 nm or less because of other factors, it is considered that the ratioof 1.5 times is the limit of practical use. As a matter of course, inorder to obtain a higher accuracy, the ratio should be made closer aspossible to 1.0 times rather than 1.5 times.

[0044] The value L2 must be 1 mm or more because of restrictions or thelike of actual processing technology of the wafer chuck 1. On theassumption, if P1/P2={circle over (1)}/{circle over (2)} is allowed tobe 1.5 times to 1/1.5 times as described above, the minimum value of thevalue L2 is 1 mm as described above, in order to control the ratio ofarea {circle over (1)} to area {circle over (2)} to 1.5 times to 1/1.5times, the following conditions are satisfied.

[0045] When the ratio is 1.5 times, L1=L2 is satisfied because L2/2+L1(=L2)=1.5 times L2 is satisfied.

[0046] When the ratio is 1/1.5 times, L1=1/6=0.17 mm because L2/2+L1(=L2/6)=L2·2/3 is satisfied.

[0047] However, since L1 is limited to about 0.2 mm due to therestrictions of processing technology, the minimum value of L1 is 0.2mm.

[0048] On the other hand, the distance L1 between the external wall 12and the closest support pin 15 a is desirably set to be up to about 1.8mm in consideration of flexure of a beam.

[0049] The reason why the distance L1 between the external wall 12 andthe closest support pins 15 a is set to be up to 1.8 mm will bedescribed below.

[0050] It is assumed that pitches of the closest support pins 15 a tothe external wall 12 and the support pins 15 b which are internallyadjacent to the closest support pins 15 a are represented by L2, anoverhang (i.e., distance between the external wall 12 and the closestsupport pin 15 a) of the peripheral portion of the semiconductor wafer11 is represented by L1, a distributed load is represented by w, alongitudinal elastic coefficient E, and a geometrical moment of inertiais represented I. In this case, a flexure y of the distal end(immediately above the external wall 12) of the overhang isapproximately expressed by the following equation:

y=w(L1)⁴/8EI+w(L1)³ L2/6E1  (Equation 2)

[0051] An Si substrate is supposed as the semiconductor wafer 11, 80 kPa(600 mmHg) are substituted to w, 1.8 mm are substituted to L1, 2 mm aresubstituted to L2, 166 MPa is substituted to E, and the thickness of thesemiconductor wafer 11 is given by 0.725 mm→I=0.0318 mm⁴. In this case,the flexure y is given by y=50 nm. In order to achieve a degree offlatness of 100 nm or less, it is proper that the factor of flexure isset to be 50 nm or less. For this reason, it is considered as thenecessary condition that L1 is 1.8 mm or less.

[0052] (Embodiment 2)

[0053] In the wafer chuck 1 according to Embodiment 1, an inflow rate ofexternal air changes depending on the distance of the gap between thesemiconductor wafer 11 and the upper surface of the external wall 12.The inflow rate of the air is expressed by Equation 1. In this case,when the gap δ is excessively large, the inflow-rate of the gasincreases to decrease the pressure in the suction chamber 13. When theinflow rate is excessively small, the semiconductor wafer 11 is broughtinto contact with the upper surface of the external wall 12, and theeffect described in Embodiment 1 may not be achieved. In addition, whenforeign material adhered to the rear surface of the semiconductor wafer11 is sandwiched between the semiconductor wafer 11 and the externalwall 12, the foreign material mounds the corresponding portion of thesemiconductor wafer 11 and may deteriorate the degree of flatness.

[0054] In an experiment, it is assumed that a semiconductor wafer 11having a diameter φ of 200 and a satin-finished rear surface is used,the width of the external wall 12 is 0.3 mm, and the gap distance is 0.5μm. About 3% of pressure in the suction chamber 13 decreases. It isassumed that an actual tolerance of a decrease in pressure is set to be10%. The value is applied to Equation 1.

[0055] When the width of an external wall is 0.3 mm, the gap δ is 0.75μm at the maximum; and when the width of the external wall is 2.0 mm,the gap 5 is 1.4 μm at the maximum, so that such values are consideredto the maximum until which the gap δ can be set.

[0056] In addition, a gap δ of 0.1 μm or more is required at the minimumsuch that the semiconductor wafer 11 is not brought into contact withthe external wall 12.

[0057] When the width of the external wall 12 is 2.0 mm or more, theflexure of the peripheral portion of the semiconductor wafer 11increases due to the influence of a vacuum pressure. For this reason, itis desirable that the width is set to be 2.0 mm or less.

[0058] (Embodiment 3)

[0059] In the wafer chuck 1 according to Embodiment 1 wherein theclosest support pins 15 a are arranged to be in one circle along theexternal wall 12 and the support pins 15 b on the second circular lineare arranged inside the closest support pins 15 a to be in one circle,the interval between the closest support pins 15 a and the support pins15 b is important to obtain the high accuracy of the degree of flatnessof the peripheral portion of the semiconductor wafer 11.

[0060] More specifically, in a semiconductor wafer 11 warped at anaverage curvature of 1/R, the semiconductor wafer 11 should be vacuumedso as to correct the warpage, so that an arrangement condition of thesupport pins 15 for performing correction at the outermost portion isrequired.

[0061] In the structure of a wafer chuck of a conventional art, theexternal wall 12 is in contact with the semiconductor wafer 11 to serveas a vacuum seal. For this reason, at the portion where thesemiconductor wafer 11 is in contact with the external wall 12, theaverage curvature of the semiconductor wafer 11 cannot be sufficientlycorrected to leave a gradient.

[0062] In this embodiment, the gradient of the semiconductor wafer 11can be decreased at the contact portions to the semiconductor wafer 11of the closest support pins 15 a to the external wall 12, and thesupport pins 15 b on the second circular line are arranged inside theoutermost pins 15 a to form in one circle such that contact surfacepressures of the closest support pins 15 a to the external wall 12 areequal to those of the other support pins 15, so that the arrangementdensity of the support pins 15 is made uniform and that the degree offlatness of a portion near the external wall 12 where a high degree offlatness cannot be easily obtained, can be improved. In this case, asdescribed above, the distance (alignment pitch L2) between the closestsupport pins 15 a to the external wall 12 and the support pins 15 b onthe second circular line is preferably set to be a value falling withina range of 1 to 2.5 mm, more preferably, 2 mm in order to easily obtainthe accuracy of the degree of flatness of the semiconductor wafer 11.

[0063] The case in which the areas of the tops of the support pins 15are set equal to each other has been described above. However, in thecase where the arrangement density of the support pins 15 is notuniform, the areas of the tops of the support pins 15 may be changeddepending on the density.

[0064] (Embodiment 4)

[0065] In each of the wafer chucks 1 according to Embodiments 1 to 3,the same operational effects as those to the external wall 12, theclosest support pins 15 a, and the support pins 15 b on the secondcircular line can be obtained for an internal wall 17 having a press-uphole 18 for a press-up pin 19 arranged a portion near the center of thewafer chuck 1 as shown in FIG. 5 and used to convey the semiconductorwafer 11, for the closest support pins 15 a to the internal wall 17, andfor the support pins 15 b on the second circular line from the internalwall.

[0066] As described above, the wafer chuck 1 described in thisembodiment prevents warpage near the external wall 12 of the chuckedsemiconductor wafer 11 and the internal wall 17 to flatly chuck thesemiconductor wafer 11. For this reason, when this embodiment is appliedto the wafer chuck 1 of an exposure system illustrated in FIG. 1, acircuit pattern having a preferable resolution can be transferred to thesemiconductor wafer 11 without changing focal lengths of the reductionlens 10 to the respective parts of the semiconductor wafer 11.

[0067] (Embodiment 5)

[0068] In the embodiment described above, the case in which thesemiconductor wafer 11 having a specific size is vacuum-fixed by oneexternal wall 12 has been exemplified. However, external walls 12 havingdifferent diameters may be arranged at once, and a plurality ofsemiconductor wafers 11 having different sizes may be vacuum-fixed.

[0069] More specifically, in the wafer chuck 1 illustrated in FIG. 6, anexternal wall 12A is arranged inside the external wall 12. In thismanner, one wafer chuck 1 can be used to vacuum-fix any one of asemiconductor wafer 11 having a small diameter corresponding to theexternal wall 12 and of a semiconductor wafer 11 having a large diametercorresponding to the external wall 12A.

[0070] In this case, the external wall 12 and the external wall 12A arenot in contact with the rear surface of the semiconductor wafer 11 eventhough any one of the semiconductor wafers 11 having the small diameterand the large diameter. For this reason, when the configuration of theinternal wall 17, the press-up hole 18, the press-up pin 19, and thelike which are illustrated in FIG. 5 is merely arranged at the centralportion of the innermost external wall 12, negative-pressure vacuum onthe entire surface of the semiconductor wafer 11 can be realized.

[0071] According to Equation 1, a linkage Q is in proportion to aperipheral length b. For this reason, in order to maintain dP at a valuerequired for vacuum, a gap δ between given walls must be smaller than agap δ between walls outside the given walls.

[0072] When semiconductor wafers having different diameters are nottargeted, and when a semiconductor wafer having a large warpage isvacuumed, the semiconductor wafer is sequentially vacuumed from thecentral portion. In this manner, problems of vacuum fault caused bywarpage can be considerably reduced. In this case, the differencebetween the levels of internal banks (peripheral walls) is set to be upto 0.3 mm which is generally considered as a limit for reliablyperforming vacuuming, and may be set to be 0.1 μm or more.

[0073] (Embodiment 6)

[0074]FIG. 7 illustrates a flow chart showing an example of a method ofmanufacturing a semiconductor device using the wafer chuck and theexposure system including the wafer chuck.

[0075] More specifically, a semiconductor substrate obtained by slicingan ingot consisting of monocrystalline semiconductor is polished tomanufacture a semiconductor wafer 11 (step 101).

[0076] In the known wafer process, a circuit pattern for a semiconductordevice is transferred to and formed on the semiconductor wafer 11 byphotolithography using the exposure system in FIG. 1. At this time, whenthe wafer chuck 1 according to each of the embodiments described aboveis used to fix the semiconductor wafer 11 to the exposure system, thecircuit pattern having a preferable resolution can be transferred to thesemiconductor wafer 11 without changing the focal lengths of thereduction lens 10 to the respective parts of the semiconductor wafer 11.

[0077] In this wafer process, the surface of the semiconductor wafer 11is flattened by a CMP (chemical mechanical polishing) technique or thelike to prevent adverse affect to an uneven upper surface of the waferbase portion in a multilevel interconnection structure or the like. Whenthe wafer chuck 1 according to each of the embodiments is used to chuckthe semiconductor wafer 11 in a polishing device for executing the CMPtechnique, high-level flattening can be performed such that maximumflexures at the respective parts of the semiconductor wafer 11 arecontrolled to 50 nm or less, reduction or the like of circuit patterndefects of the upper layer caused by the unevenness or the like of thebase can be realized (step 102).

[0078] In the semiconductor wafer 11 on which a large number ofsemiconductor devices are formed at once by the above wafer process, thefunctions of the respective semiconductor devices are inspected by awafer probe or the like (step 103). Furthermore, in the dicing step forthe semiconductor wafer 11, the plurality of semiconductor devices areseparated into independent chips (pellets) (step 104), and only chipswhich are determined as nondefective chips in the inspection step instep 103 are packaged (step 105).

[0079] In this manner, semiconductor devices serving as products arecompleted. In this embodiment, as described above, the semiconductorwafer 11 is chucked by the wafer chuck 1 with a high degree of flatnessand exposed. For this reason, high accuracy of focal lengths of thereduction lens 10 to the respective parts of the semiconductor wafer 11is achieved, and improvement in transfer accuracy of a circuit patterncan be realized.

[0080] When the wafer chuck 1 according to this embodiment is applied tothe CMP step, reduction of defects such as disconnection in amulti-layered interconnection structure can be realized by high-levelflattening of the semiconductor wafer 11 in the CMP step. As a result, ahigh yield in the steps in manufacturing semiconductor devices can beachieved.

[0081] The present made by the present inventor has been concretelydescribed on the basis of the embodiments. However, the presentinvention is not limited to the embodiments, and various changes andmodifications can be effected without departing from the spirit andscope of the invention as a matter of course.

[0082] In the above description, the invention made by the presentinvention has been explained with respect to an optical exposure systemin the field of the invention which is the background of the invention.However, the present invention is not limited to the optical exposuresystem, and the present invention can be applied to an electron beamexposure system, and not only these exposure systems, but also varioussemiconductor manufacturing devices and semiconductor inspection deviceswhich must flatly chuck semiconductor wafers.

[0083] In addition, the present invention can be applied to not only thesteps in manufacturing a semiconductor device but also the steps inmanufacturing liquid crystal or the like.

INDUSTRIAL APPLICABILITY

[0084] Effects obtained by typical one of the aspects of the inventiondisclosed in this application will be briefly described below.

[0085] (1) More specifically, according to the wafer chuck of thepresent invention, when external air is sucked into a suction chamber bya space between a semiconductor wafer and the upper surface of anexternal wall, a pressure loss caused by a viscosity resistance toestablish a vacuum seal between the suction chamber and the outside, andthe semiconductor wafer can be vacuum-chucked by only support pins. Inthis manner, uniform vacuum chucking can be performed in an entire areasubject to wafer vacuuming, and vacuum chucking can be performed with anextremely high degree of flatness.

[0086] (2) According to the wafer chuck of the present invention, aneffect that semiconductor wafers having various diameters can bevacuum-chucked by one wafer chuck can be achieved.

[0087] (3) According to an exposure system using the wafer according tothe present invention, since the degree of flatness of a chuckedsemiconductor wafer including its peripheral portion increases, focallengths do not change in the entire area of the semiconductor wafer, anda circuit pattern having a preferable resolution can be transferred tothe semiconductor wafer.

[0088] (4) When a wafer chuck according to the present invention is usedin a semiconductor wafer polishing device, a polished surface having ahigh degree of flatness can be obtained.

[0089] (5) According to the above (3) and (4), in a method ofmanufacturing a semiconductor device using the wafer chuck of thepresent invention, non-defective semiconductor chips can be manufacturedin the entire area of the semiconductor wafer, and an yield ofsemiconductor devices can be increased.

What is claimed is:
 1. A wafer chuck for flatly vacuum-chucking asemiconductor wafer supported on support pins by suction with a suctionchamber at a negative pressure applied thereto, said suction chambersurrounded by a first peripheral wall, wherein: an upper surface of thefirst peripheral wall is formed to be lower than an upper surfaces ofthe support pins, and the upper surface of the first peripheral wall isnot in contact with the semiconductor wafer; and a first distancebetween the first peripheral wall and first closest support pins of thesupport pins is set to be shorter than a second distance between thefirst support pins and second support pins positioned inside the firstsupport pins.
 2. A wafer chuck according to claim 1, wherein the firstdistance is not less than 0.2 mm and not more than 1.8 mm.
 3. A waferchuck according to claim 1, wherein a difference between the level ofthe upper surface of the first peripheral wall and the level of theupper surfaces of the support pins falls within a range of 0.1 μm to 1.4μm.
 4. A wafer chuck according to claim 1, wherein the first supportpins are arranged to make one circle along the first peripheral wall,and the second support pins on a second circular line are arrangedinside the closest support pins with a distance falling within a rangeof 1 mm to 2.5 mm.
 5. A wafer chuck according to claim 1, wherein atleast one second peripheral wall is arranged inside the first peripheralwall, a positional relationship between the first support pins and thesecond peripheral wall inside or outside the second peripheral wall isequivalent to a positional relationship between the first peripheralwall and the first support pins in the wafer chuck according to claim 1,2, 3, or
 4. 6. A wafer chuck according to claim 5, wherein a differencebetween the level of the upper surface of the second peripheral wall andthe level of the upper surface of the first support pins falls within arange of 0.1 μm to 0.3 mm.
 7. A wafer chuck according to claim 5,wherein the support pins are not arranged inside the second peripheralwall, and a pressure inside the second peripheral wall is theatmospheric pressure.
 8. An exposure system including a wafer chuck onwhich a semiconductor wafer is placed; exposure light source; and aprojection optical system for irradiating exposure light emitted fromthe exposure light source, passing through an exposure original on thesemiconductor wafer, wherein the wafer chuck according to claim 1, 2, 3,4, 5, 6, or 7 is used as the wafer chuck of the exposure system.
 9. Amethod of manufacturing a semiconductor device which performs waferprocesses including a polishing process and a photolithography processto a semiconductor wafer to form a semiconductor device, wherein thewafer chuck according to claim 1, 2, 3, 4, 5, 6, or 7 is used for, atleast, any one of a wafer chuck for chucking the semiconductor wafer inthe polishing process and of a wafer chuck in an exposure system used inthe photolithography process.
 10. A method of manufacturing asemiconductor device according to claim 9, characterized in that thepolishing process is a chemical mechanical polishing (CMP) process.